Automotive MCUs for SiC charging

“Typical automotive MCUs in the market today cannot execute the charging-control algorithms at a rate that can support the higher SiC switching frequencies,” claimed ST. “Instead, additional DSP chips are needed specifically to handle the control loop.” The new parts are “automotive-qualified MCUs that perform the high-speed control-loop processing alongside general control in the same chip”.

The company is only revealing information in general terms – the parts are sampling to lead customers now and only due for production next year. AEC-Q100 automotive qualification is in the pipeline.

The family name is SR5E1, and the two parts named  so far are: SR5E1E3 (14 x 14mm TQFP100), and SR5E1E7 (24 x 24mm LQFP176) – no further information has been revealed to differentiate between the two.

The super-set of family characteristics includes ISO 26262 ASIL-D functional safety capability and, towards this, processing can be through a pair of 32bit Arm CortexM7 cores  running in parallel or in lock-step. Double-precision floating point is offered, and L1 cache and DSP instructions. There are two DMA engines, also in lock-step.

The parts are equipped for over-the-air upgrade, with dual image storage (two flash banks, each of 960kbyte) and cryptography. The hardware security module is built around a Cortex M0+ with its own ram and flash, and a hardware accelerator for symmetric cryptography.

96kbyte of data flash is provided (of which 32kbyte is dedicated to hardware security), and well as 488kbyte of ram spread across various functions.

Of the hardware dedicated to fast power control with SiC or GaN power devcices, two of the 12 timers are described as ‘high-resolution and complex waveform builder” by the company, and there is hardware cordic acceleration for trigonometric functions. Five SAR ADCs area available (and two ΣΔ ADCs) plus eight comparators. Sadly, no detailed information has been revealed.

For analogue waveform production, there are DACs delivering two buffered external channels and eight un-buffered channels.

Communications are covered by four CAN modules (supporting flexible data rate – ISO CAN-FD), three LIN-capable UARTs, four SPI interfaces (two multiplexed with I²S) and two I²C modules.

Debug and trace is built around Arm CoreSight, but has other options. Software interoperability is via Autosar 4.3.x.

The SR5E1 product page is here